1. Field of the Invention
The invention generally relates to a Schottky barrier diode structure, and, more particularly, to a silicon-on-insulator based Schottky barrier diode structure and method of forming the structure.
2. Description of the Related Art
Back-gate complimentary metal oxide semiconductors (CMOS) devices offer two advantages for 32 nm technology both of which are related to the ability to use the back-gate to set threshold voltage (Vt). The first is that channel doping to set Vt can be reduced or eliminated. Using a back gate to set Vt instead of channel doping reduces Vt fluctuation, which is a severe challenge for the 32 nm integrated circuit technology node. The second is that each individual die can be optimized for Vt depending on measured chip (subthreshold) leakage and performance. This will increase performance, decrease power, and improve the manufacturing window size. Unfortunately a relatively thick back gate dielectric layer is desired in order to minimize additional parasitic capacitance and optimize drive current. This thick back gate dielectric layer results in the need for relatively large voltages required on the back gate to control Vt (up to ˜7V). Since on-die voltage supply (Vdd) is expected to be only ˜1V, voltage multipliers are necessary. Multipliers using pn junction diodes are standard for voltage multiplication. However, the forward voltage for pn junction diodes is relatively large in silicon (˜0.6V), so such pn junction diodes prove to be very ineffective. It would be advantageous to provide a diode with a lower forward voltage, such as a Schottky barrier diode with a forward voltage drop of ˜0.3V, that can be manufactured efficiently and economically using currently available silicon-on-insulator (SOI) processing flows.